The present invention relates to an architecture for providing a high speed programmable counter. In particular, the present invention relates to a high speed counter that can be programmed to divide by a wide range of values.
Programmable counters are used in a variety of electronic devices. In one application, programmable counters are used as frequency dividers, in which an output of the programmable counter is a periodic signal having a frequency equal to some fraction of the frequency of the input signal. However, the value by which an input signal can be divided is limited when existing high speed programmable counters are used.
Binary counters formed from multiple stages in which each stage divides by a power of two are known. In addition, binary counters capable of dividing by any desired number are known. However, the maximum speed of such counters is severely limited.
In order to provide a higher speed counter, it is possible to use a high speed prescaler that divides the input frequency by a fixed number, usually a power of two. However, in such a counter, the modulus that the counter may divide by is limited to multiples of the prescaler value.
Still another approach is to use a dual modulus prescaler followed by a lower speed counter stage. In such an arrangement, illustrated in FIG. 1, the high speed counter 100 consists of a high frequency, dual modulus prescaler 104, a low frequency programmable counter, connected as a single shot 108, and a low frequency programmable counter 112. The high speed counter 100 in FIG. 1 receives a high frequency input signal 116 at an input to the high frequency prescaler 104. An output 120 of the prescaler 104 is asserted for every nth or (n+1)th cycles of the input 116. The low frequency clock output 120 is provided to both the single shot 108 and the programmable counter 112. A carry output 124 is generated by the programmable counter 112 for every mth clock cycle received from the low speed output 120 of the prescaler 104. The output 128 of the single shot 108 is provided to the modulus control input 132 of the prescaler 104 to control whether the prescaler 104 divides by n or n+1.
The high speed counter 100 illustrated in FIG. 1 is limited in the moduli by which the counter can divide. That is, in a circuit 100 using a prescaler 104 that can divide by either n or n+1, the modulus can have only certain values below n*(nxe2x88x921). In particular, in a prescaler that comprises a dual modulus counter, with the moduli n and n+1, one period of the low speed counter can be extended by only one high speed clock cycle. Therefore, the low speed counter 112 must have at least R periods in order to accommodate every possible remainder up to the value of R. This sets the lower limit of the possible contiguous moduli to n*(nxe2x88x921). For example, a high speed counter 100 using an 8/9 prescaler 104 can divide by 16, 17 or 18 if the low frequency programmable counter 112 is programmed to divide by 2. The counter 100 can also be programmed to divide by
24, 25, 26, 27,
32, 33, 34, 35, 36,
40, 41, 42, 43, 44, 45 etc.
Only after 55 can a counter 100 using an 8/9 prescaler divide by any value. Accordingly, existing high speed counters have been limited in their applications.
In addition, relatively complicated calculations must be performed in order to determine how many times the prescaler must count to n and how many times it must count to n+1 to achieve the desired modulus of division. For example, to divide an input signal by i=1111 using an n=32/33 prescaler, the following calculations are performed:
M=integer part of i/n=int(1111/32)=34
R=ixe2x88x92n*M=1111xe2x88x9234*32=23
J=Mxe2x88x92R=34xe2x88x9223=11
So i=R*(n+1)+J*n
Or 1111=23*33+11*32.
The above calculations indicate that a prior art counter using a dual modulus prescaler must be programmed to count 23 times to 33, and to count 11 times to 32. Accordingly, the counter 112 will be programmed to divide the low frequency clock output 120 by 34, and the single shot 108 will generate a positive pulse for 11 of the output pulses.
For the above stated reasons, it would be advantageous to provide a high speed counter capable of dividing by relatively small moduli. In addition, it would be advantageous to provide such a counter that was easy to program.
In accordance with the present invention, a method and apparatus for providing a high speed programmable counter is disclosed. The present invention generally allows an input signal to be divided by any number greater than or equal to J*2n, where n is the number of bits of a high speed prescaler provided as part of the high speed counter and J is a small number, e.g. 1 or 2. In addition, the present invention allows the modulus of division to be directly loaded into the counter.
According to one embodiment of the present invention, the high speed programmable counter comprises a programmable high speed prescaler followed by a programmable low speed counter. In particular, the programmable high speed prescaler receives a signal having a frequency to be divided, and outputs a low frequency output. The low speed counter receives the low frequency output, and generates a counter output signal having a frequency equal to the input frequency divided by the modulus of division and a control signal. The value by which the high speed prescaler divides the input signal is determined by the n least significant bits of the modulus of division. The value by which the low speed counter divides the signal received from the high speed counter is determined by the m most significant bits of the modulus of division.
Generally, a counter according to an embodiment of the present invention consists of a low speed counter and a high speed prescaler. The low speed m bit counter has m data bit inputs, one clock input, one load input and one CARRY output which divides the clock input by the number represented in binary form by the m most significant bits of the i modulus. This counter is preceded by a high speed multi-modulus counter, a prescaler, with n data bit inputs, one clock input, one trigger input and one output, where the n bits are the least significant bits of the i modulus. The low speed counter is reloaded by its own CARRY output and is clocked by the high speed clock divided by the prescaler (i.e. by the output of the high speed prescaler). The modulus of the prescaler is at least 2n and at most 2n+2nxe2x88x921, where the 2nxe2x88x921 is equal to the maximum number defined by the n bits and which is also equal to the remainder R defined by the equation
R=ixe2x88x92n*m.
In accordance with an embodiment of the present invention, the high speed prescaler can be programmed to produce one output pulse for from every 2n to every 2n+(2nxe2x88x921) cycles of the signal to be divided. In accordance with a further embodiment of the present invention, the high speed prescaler is formed from 2n D flip-flops and n NAND gates.
In accordance with another embodiment of the present invention, a method for implementing a high speed programmable counter is provided. According to the method, the m most significant bits of an m+n bit databus carrying a value equal to the modulus of division of the counter are provided to the low speed counter.
In accordance with the present invention, the high speed prescaler is a multi-modulus counter that can be programmed to produce one output pulse for from every 2n to every 2n+(2nxe2x88x921) cycles of the signal to be divided, so that J*2n is the lowest possible limit, where J is any integer value greater than zero, including a low number like 2 or even 1.
In accordance with another embodiment of the present invention, the m most significant bits of an m+n bit databus carrying a value equal to the desired modulus of division are provided to the low speed counter. The m most significant bits establish a starting count value for the low speed counter. The n least significant bits of the m+n bit databus are provided to a high speed prescaler. The method according to this embodiment of the present invention allows the high speed programmable counter to divide by any number greater than a low multiple of 2n. According to another embodiment of the present invention, the modulus of division may be any number equal to or greater than 1. Furthermore, this method allows the modulus of division to be loaded into the high speed programmable counter in binary form, without requiring ancillary calculations.
Additional advantages of the present invention will become readily apparent from the following discussion, particularly when taken together with accompanying drawings.